1. Field of the Invention
The present invention relates to a semiconductor device with a mask ROM (mask programmable ROM) which is programmable by means of a mask.
2. Prior Art
Patent Document 1, for example, discloses a conventional semiconductor device. Paragraphs 0002 to 0006 on page 2 and FIG. 2 of this document disclose the configuration of a contact programming mask ROM.
FIG. 9 is a circuit diagram showing the configuration of the above described contact programming mask ROM. In a contact programming ROM, whether or not the drain of a memory cell transistor is connected to a bit line respectively corresponds to “0” or “1” of memory data. Such a mask ROM is programmable by means of a mask.
A conventional semiconductor device is, as shown in FIG. 9, formed of a memory cell array 1, a column decoder 2, a sense amplifier 3, a transistor for charging 4, an output buffer circuit 6 and a latch circuit 15.
Memory cell array 1 has a configuration wherein a number of memory cells Mij (i=1 to m, and j=1 to n) made of N type MOS transistors are arranged in matrix form. The gates of memory cells Mij having the same number of i, that is to say, the memory cells aligned in the same row, are connected to the same word line selection signal WLi (i=1 to m). In addition, the sources of these memory cells Mij are connected to a wire at the grounding potential. These drains are connected to bit lines BLj (j=1 to n) in the case where the memory data of the memory cells is “0,” and are made in the floating condition in the case where the memory data of the memory cells is “1.”
Column decoder 2 is formed of N type MOS transistors Cj (j=1 to n). The drains of N type MOS transistors Cj (j=1 to n) are connected to each other, the sources are connected to bit lines BLj (j=1 to n), and the gates are connected to column selection signals CLj (j=1 to n), respectively.
Sense amplifier 3 is formed of a buffer circuit. The input thereof is connected to the drains of N type MOS transistors Cj (j=1 to n) that form column decoder 2, and the output is connected to an input end D of latch circuit 15.
Transistor for pre-charging 4 is formed of a P type MOS transistor. The gate of transistor for pre-charging 4 is connected to a charge control signal PCLK, the source is connected to a power supply terminal having a power supply potential, and the drain is connected to the drains of N type MOS transistors Cj (j=1 to n) that form column decoder 2.
The input of output buffer circuit 6 is connected to an output end Q of latch circuit 15, and the output is connected to an output end OUT.
The input terminal of latch circuit 15 is connected to the output end of sense amplifier 3, so that a signal of the same logic as the signal of input end D is outputted to output end Q when a latch control signal LCLK is “L” and a latch control signal NLCLK is “H.” In addition, the output condition of output end Q is maintained when latch control signal LCLK is “H” and latch control signal NLCLK is “L.”
The operation of reading data in memory cell M11, for example, in the semiconductor device that is formed as described above is described in reference to the timing chart of FIG. 10.
Column selection signal CL1 from among column selection signals CLj (j=1 to n) is set at the “H” level, and column selection signals CL2 to CLn are set at the “L” level. As a result of this, N type MOS transistor C1 from among N type MOS transistor Cj (j=1 to n) that form column decoder 2 is set at the ON condition, and the other N type MOS transistors C2 to Cn are set at the OFF condition.
Next, pre-charge control signal PCLK is set at the “L” level during a certain period of time Tp, so that transistor for pre-charging 4 is set to the ON condition for this period of time Tp. As a result of this, bit line BL1 is charged to the “H” level.
After bit line BL1 has been set at the “H” level, word line selection signal WL1 from among word line selection signals WLi (i=1 to m) is switched from the “L” level to the “H” level, and the other word line selection signals WL2 to WLm are maintained at the “L” level.
As a result of this, in the case where the drain of memory cell M11 is connected to bit line BL1, the charge that has charged bit line BL1 is discharged by memory cell M11 so that bit line BL1 becomes of the “L” level and the input of sense amplifier 3 becomes of the “L” level. In addition, as for latch control signals LCLK and NLCLK of latch circuit 15, when a word line from among word line selection signals WLi (i=1 to m) is selected, latch control signal LCLK is at the “L” level and latch control signal NLCLK is at the “H” level. Accordingly, the output of sense amplifier 3 becomes of the “L” level and output Q of latch circuit 15 becomes of the “L” level, so that “L” is read out from output end OUT of output buffer circuit 6 (shown by broken lines in FIG. 10).
In addition, in the case where the drain of memory cell M11 is not connected to bit line BL1, the charge that has charged bit line BL1 is not discharged by memory cell 11, so that bit line BL1 maintains the “H” level and the input of sense amplifier 3 also becomes of the “H” level. In addition, as for latch control signals LCLK and NLCLK of latch circuit 15, when a word line from among word line selection signals WLi (i=1 to m) is selected, latch control signal LCK is at the “L” level and latch control signal NLCLK is at the “H” level. Accordingly, the output of sense amplifier 3 becomes of the “H” level and output Q of latch circuit 15 becomes of the “H” level, so that “H” is read out from output end OUT of output buffer circuit 6 (shown by solid lines in FIG. 10).
Patent Document 1: Japanese Unexamined Patent Publication H6 (1994)-176592 (page 2, FIG. 2)
Patent Document 2: Japanese Unexamined Patent Publication S61 (1986)-255035 (pages 1 and 2, FIG. 2)
Patent Document 3: Japanese Unexamined Patent Publication H4 (1992)-34799 (pages 1 and 2, FIG. 3)
Conventional semiconductor devices have the following problems. The relationship between memory data “0” or “1,” and whether or not the drain of a memory cell transistor is connected to a bit line, is fixed. As a result of this, in the case where there are a large number of “0” in the memory data, there are a large number of connections between the drains of memory cell transistors and bit lines.
In recent years, the number of steps for wiring between the drains of memory cell transistors and bit lines, as well as the number of steps for creating via holes, have increased in the structure of memory cells due to an increase in the number of layers for wiring which are to be processed during a short TAT (turn-around time). Furthermore, it becomes easy for the problem of poor connection to occur in the steps for wiring and in the steps for creating via holes for the connection between the drains of memory cell transistors and bit lines, due to miniaturization of the processed object. As a result of this, the yield is lowered when there are a large number of connections between the drains of memory cell transistors and bit lines.
Therefore, a method for reducing the number of connections between the drains of memory cell transistors and bit lines by adding a circuit for inverting the data behind the sense amplifier of the mask ROM so as to change the logic of the connections of memory cell transistors to bit lines and the memory data has been proposed.
However, a problem arises where a control circuit must be added. In addition, there is a problem where it is difficult to control information at the time of analysis, whether or not the drains of memory cell transistors are connected to bit lines for data “0,” because the logic differs, depending on the mask ROM mounted on the semiconductor device, and depending also on the respective outputs. In addition, in the case where the IP (intellectual property) of the mask ROM of which the logic can be changed is not available, a problem arises where the number of connections between the drains of memory cell transistors and bit lines cannot be reduced.